For a semiconductor package substrate used in an electronic device, there have typically formed a plurality of through holes, such as plated through holes (PTHs), vias and blind holes, through the substrate in order to shorten a transmission path for chip signals. Further, at least a power plane and a ground plane are provided between multiple stacked layers of the substrate to enhance the electrical performance of a semiconductor package with the substrate. Accordingly, current may flow from the power plane of the substrate to a chip mounted on the substrate and then flow to the ground plane of the substrate via the plated through holes (having metal layers plated on walls of the through holes), thereby improving the electrical quality of the chip.
When the chip signals are transmitted to an inner circuit of the substrate, inner impedance of the inner circuit is generated. In order to ensure the consistency between the inner impedance of the substrate and outer impedance of an outer circuit externally connected to the electronic device, it usually requires considering electrical functions for both signal and power distributions in the device electrical design. One common transmission circuit design relates to a structure adopting a differential pair.
The so-called “differential pair” involves an improved technique for overcoming a drawback of insufficient transmission distance and strength provided by a single signal line during parallel data transmission by bus lines. This technique allows each bit signal to be transmitted over two signal lines having inverted phases in a way of having paired complementary signals for data transmission. The use of paired complementary signals results in greater tolerance to external interference and reduction of crosstalk, echo and noise. Further, the complementary characteristic of the differential-pair signals also reduces the drifting of ground potential signals, prevents the occurrence of a ground bounce, and thereby improves the ground performance of the electronic device.
However, when the chip signals are transmitted through bonding wires, conductive circuits, the plated through holes, the ground plane (or power plane) to solder balls implanted at a bottom surface of the substrate, impedance of the chip signals is decreased due to an increase in a capacitance effect generated between the metal layers plated on the walls of the through holes and the ground/power plane. As a result, integrated circuit (IC) output impedance (i.e. external impedance) from the substrate is smaller than loop impedance (i.e. internal impedance) of the chip, thereby resulting in a return loss during signal transmission. The return loss becomes more serious when the semiconductor package is operating at a high frequency. Accordingly, the present applicant has proposed an improvement, which was filed in Taiwan and granted as Taiwan Patent No. I237381 directed to a semiconductor package substrate for maintaining impedance consistency.
As shown in FIG. 1, a semiconductor package substrate disclosed in Taiwan Patent No. I237381 comprises an opening 13 formed through electrically integrated layers 11, 12 at a position corresponding to two adjacent conductive through holes 100, 101 that are formed as a differential pair, such that the conductive through holes 100, 101 are exposed through the opening 13. When the chip signals ate transmitted from an inner circuit layer 104 through the conductive through holes 100, 101 and the electrically integrated layers 11, 12 to solder balls (not shown) implanted at a bottom surface of the substrate and output from the solder balls, the opening 13 enlarges the spacing between the conductive through holes 100, 101 and the electrically integrated layers 11, 12, such that the chip signal impedance and the IC output impedance can be maintained consistent with each other.
However, the above technology may not be suitable for a substrate in a multi-layer ball grid array (BGA) semiconductor package disclosed in U.S. Pat. No. 5,741,729. This is because such substrate is usually formed with a plurality of ball pads at a bottom surface thereof, and the ball pads are considered as a large area conductor for a signal transmission path, such that a capacitance effect is easily generated between the ball pads and an overlying power/ground plane, thereby leading to mismatch in circuit impedance and degrading the electrical performance of the semiconductor package.
Therefore, the problem to be solved here is to develop a semiconductor package substrate to overcome the above drawbacks in the prior art.